 SU.HARDW.PC.MOTHERBOARD (2:5020/299)  SU.HARDW.PC.MOTHERBOARD 
 From : Igor Wihanski                       2:5030/87.53    Sat 27 May 95 00:29 
 Subj : SIS471                                                                  


᫨ -    p  SIS471, pp, ᫨
 ⠯   ⠭ ,   p  p諥:

Hp pp   IO-p 22h,  /⠥  p 23h.

Ŀ
p      pp              祭          
Ĵ
50h 3  Cache WB/WT         0 - WT,      1 - WB      
    5  DRAM Write CAS      0 - 2T,      1 - 1T      
    6  bit0 Dram Speed    0 - Slowest, 1 - Slower, 
    7  bit1               2 - Faster,  3 - Fastest 
                                                    
51h 0  Cache Burst Read    0 - 1T,      1 - 2T      
    1  Cache Write Cycle   0 - 3T,      1 - 2T      
    2  DRAM Interleave     0 - Disable, 1 - Enable  
    3  Cache Interleave    0 - Disable, 1 - Enable  
    4  bit0 Cache Size    0 - 32k,     1 - 64k,    
    5  bit1               2 - 128k,    3 - 256k    
    6   ? (bit3 Cache Size)0 - ?                    
    7  Cache Active        0 - Disable, 1 - Enable  
                                                    
52h 0  Shadow (C000-C7FF)  0 - Disable, 1 - Enable  
    1  Shadow (C800-CFFF)  0 - Disable, 1 - Enable  
    2  Shadow (D000-D7FF)  0 - Disable, 1 - Enable  
    3  Shadow (D800-DFFF)  0 - Disable, 1 - Enable  
    4  Shadow (E000-E7FF)  0 - Disable, 1 - Enable  
    5  Shadow (E800-EFFF)  0 - Disable, 1 - Enable  
    6  Shadow Write        0 - Enable,  1 - Disable 
    7  Shadow (C000-FFFF)  0 - Disable, 1 - Enable  
                                                    
53h 4  Video Shadow Cache  0 - Disable, 1 - Enable  
    5  System Shadow Cache 0 - Disable, 1 - Enable  
                                                    
54h0-7 Memory Hole Size    0 - '0000',  1M- 'D0F0', 
55h0-7                     2M- 'E0E0',  4M- 'F0C0'  
                                                    
57h 3  Fast Reset Lat.     0 - 2mks,    1 - 6mks    
    4  Fast Reset Emul.    0 - Disable, 1 - Enable  
                                                    
58h 0  VLB RDY             0 - Sync.    1 - Transp. 
    1  Latch VLB           0 - T3,      1 - T2      
    5  Hidden Refresh      0 - Disable, 1 - Enable  
    6  DRAM Write WS       0 - 1ws,     1 - 0ws     
                                                    
59h 7  System Speed        0 - High,    1 - Low     
                                                    
5Bh 1  Memory Relocate     0 - Enable,  1 - Disable 
                                                    
60h 5  bit0 ISA Clock     0-7MHz, 1-1/10 * CLK2,   
    6  bit1                2-1/8, 3-1/6,  4-1/5,   
    7  bit2                5-1/4, 6-1/3, 7-1/2     
                                                    
61h 4  bit0 \ 8bit-IO RT    00 - 16 BusClk, 01 - 11,
    5  bit1 /               10 - 7,         11 - 4. 
    6  bit0 \ 16bit-IO RT   00 - 8 BusClk,  01 - 5, 
    7  bit1 /               10 - 3,         11 - 2. 
                                                    
75h 1  MA Drive Cap.       0 - 12ma,    1 - 24ma    


p p ""    p, ⠬  ⠪ p...
᫨  -    p,   訡  ⮩, .
p ᭨  ᥡ  ⢥⢥...

Igor

--- GoldED 2.50.Beta5+
 * Origin: Idler BBS (812)225-2946 (01:00-09:00) (2:5030/87.53)
