 SU.HARDW.SCHEMES (2:5020/299)  SU.HARDW.SCHEMES 
 From : Alexej Vladimirov                   2:5100/22.1     Sat 20 Jan 96 13:41 
 Subj : X24C16S                                                                 


- http:\\www.xicor.com
     .pdf .
  p ᮢ:

____________________________________________________________________________
  "Xicor data book", 1992. P. 2-71...2-82

X24C16 - 16K (2048x8) CMOS Serial Electrically Erasable PROM.
Pin configuration:
      =====
 A0 -|1 U 8|- Vcc
 A1 -|2   7|- ^WC
 A2 -|3   6|- SCL
Vss -|4   5|- SDA
      =====
    DIP, SOIC

DC Characteristics:
                                 min     max             conditions
Supply voltage X24C16            4.5     5.5
               X24C16-3.5        3.5     5.5
               X24C16-3          3.0     5.5
               X24C16-2.7        2.7     5.5
Power supply current (read), mA          1.0
                     (write), mA         3.0
Standby current, uA                      150            Vcc= 5.5 V
                                         50             Vcc= 3.3 V
Input leakage current, uA                10             Vin= 0V to Vcc
Output leakage current, uA               10             Vout= 0V to Vcc
Output low voltage, V                    0.4            Iol= 3 mA

AC Characteristics:
                                                         min   max   conditions
SCL Clock frequency, kHz                       Fscl            100
Noise suppression time, ns                     Ti              100
SCL low to SDA data out valid, us              Taa       0.3   3.5
Time the bus must be free before a new
transmition can start, us                      Tbuf      4.7
Start condition hold time, us                  Thdsta    4.0
Clock high period, us                          Thigh     4.0
Clock low period, us                           Tlow      4.7
Start condition setup time, us                 Tsusta    4.7
Data in hold time, us                          Thddat      0
Data in setup time, ns                         Tsudat    250
SDA and SCL rise time, us                      Tr                 1
SDA and SCL fail time, ns                      Tf               300
Stop condition setup time, us                  Tsusto    4.7
Data out hold time, ns                         Tdh       300
Power-up to read operation, ms                 Tpur        1
Power-up to write operation, ms                Tpuw        5
Write cycle time, ms                           Twr         5     10


Bus timing:

              | Tf|       | Thigh  |     Tlow    |            | Tr|
        ______|   |       | ______ |             | _____      |   |___________
      |/       \| |       |/      \|             |/     .     | |/
SCL__/|         |\|______/|        |\___________/|       .....|/|
      |  |      |                  |             |              |
Tsusta|<>|Thdsta|                  |Thddat|Tsudat|        Tsusto|<>| Tbuf  |
________ |      |       ___________|_____ | ___________......      | _____ |
        \|      |      /           |     \|/                       |/     \|
SDA IN   |\_____|____/_____________|_____/|\___________........___/|       |\_
                |                  |
                | Taa |            |Tdh|
_____________________ | ______________ | _____________________________________
\ /\ /\ /\ /\ /\ /\ /\|/              \|/
SDA OUT_\/_\/_\/_\/_\/|\______________/|\_____________________________________


Current address Read (SDA line):

 S                                     S
 T         A A A     D D D D D D D D   T
 A 1 0 1 0 2 1 0 1 0 7 6 5 4 3 2 1 0 1 O
 R                 A                   P
 T                 C
                   K

Random Read (SDA line):

 S                                     S                                     S
 T         A A A     W W W W W W W W   T         A A A     D D D D D D D D   T
 A 1 0 1 0 2 1 0 0 0 7 6 5 4 3 2 1 0 0 A 1 0 1 0 2 1 0 1 0 7 6 5 4 3 2 1 0 0 O
 R                 A                 A R                 A                   P
 T                 C                 C T                 C
                   K                 K                   K



Byte Write (SDA line):

 S                                                       S
 T         A A A     W W W W W W W W   D D D D D D D D   T
 A 1 0 1 0 2 1 0 0 0 7 6 5 4 3 2 1 0 0 7 6 5 4 3 2 1 0 0 O
 R                 A                 A                 A P
 T                 C                 C                 C
                   K                 K                 K

A0, A1, A2 - device address (pin 1,2,3). System cold have up to 8 X24C02
on the bus.

W0...W7 - word address

D0...D7 - data
___________________________________________________________________________


Alexej

--- GoldED/2 2.50+
 * Origin: * AV_Point - Riga, Latvia * (2:5100/22.1)


